LTspice Lesson 4a: Generate Waveforms used in Electric Circuits: SINE

Kashif Javaid

Instead of cut-and-paste of LTspice help file as some of LTspice tutorials on the internet has done, I think best way to learn nitty and gritty of this tool is to solve a circuit by hand, predict it’s output by varying some parameter and verify it using LTspice. If it’s complicated circuit, often it can broken down to simpler block.

LTspice has various options to generate pulses, sine waves, exponential and piece wise linear (PWL) and built-in Frequency modulation sources as shown in below diagram.

Screen Shot 2019-03-10 at 9.07.52 PM.png

We will look at one source at a time and look at the relevant circuit, solve it by hand and predict it behavior and verify it using LTspice. In the process we will master each source syntax.

Generate a Sine wave:

Generating a sine wave is easy and given by following equation 1:


Screen Shot 2019-10-14 at 4.00.46 PM.png

Screen Shot 2019-10-14 at 3.53.50 PM.png

All illustrated version is shown in the plot below:

Screen Shot 2019-10-14 at 3.23.50 PM.png

True to spirit of these tutorials, we will predict the output using calculation and intuition. Then we will verify it using LTspice.

Total Response of a RC circuit to suddenly apply sinusoid:

In this example, we will simulate output response of RC circuit for a sinusoid input. Typical approach is to convert the circuit into frequency domain and find the stead state response. In order to capture the total response which include both transient and steady state responses, I chose to employ a harder approach to calculate the response to suddenly applied sinusoid. First I wanted to review my math, but most importantly both calculation and simulation will allow us to capture the total response to suddenly applied sinusoid input. I calculated the total response from following differential equation of the RC circuit:

Screen Shot 2019-11-20 at 9.54.21 PM.png

where Vs=cos(2*pi*f*t)

The complete solution for this differential equation for the sinusoid input consist of both transient and steady state components:

Screen Shot 2019-11-20 at 9.55.10 PM.png

If you are interested in math behind it, check out here, but important thing to note is that there will be some interesting transient effects which dies out as time progresses. I want to capture this behavoir using simulation and possible on the bench. For capturing transient behavior we need to define the initial condition on the capacitor using              .ic V(vc)=0V command along with uic directive. uic is stand for Use Initial Conditions. This directive need to be used carefully as DC operating point analysis is typically performed before starting the transient analysis, but this command can bypass it. So if you have a situation where a voltage source is hooked up directly to a cap and we used similar initial condition as ic V(vc)=0V and uic, then LTspice will complain as voltage on the cap cannot be change instantaneously because this will require a infinite amount of current (I = C dv/dt).

Results from the formula, simulation and bench are shown below. The agreement between formula and simulation is excellent as it should be. The bench results show similar behavior and close to theoretical value.

Screen Shot 2019-11-20 at 9.33.36 PM.png

The difference between math/simulation and bench on peak numbers are most likely due component tolerances as wells as my scope cursor resolution. The important thing to note is the shape of the actual bench response from real component is very close our theoretical results:

Screen Shot 2019-11-20 at 9.36.10 PM.png

In conclusion, steady state response can be found very easily using simple Laplace transformation, but I wanted to capture what happens during initial time period and how can we model it using the LTspice while creating a sinusoid as a stimulus. In general, a flexible sinusoid (sine or cos) with option to vary different parameters can be created using the LTspice SINE directive.




Posted in LTspice for EE students | Tagged , | Leave a comment

LTspice Lesson 3: Transmission lines part 1

Kashif Javaid

In this lesson we will focus on a single element Lossless Transmission line (T-line) as shown in Figure 1. Lossless T line simulation will be introduced here. One of the goal of these lessons are to give out practical examples from real world. Transmission line model real world signals very well. This lesson focus on the Lossless T-line where no power gets dissipated during transmission. In a future lesson, we will focus on lossy line and loss mechanics.

Screen Shot 2019-08-26 at 8.36.03 PM

Figure 1: LTspice symbol

What is transmission line? A transmission line is any conductor along with a return path where a signal travel from source to load. Because of finite speed of light, a signal takes a finite amount of time called Time Delay (TD) to go from source to load. Signal sees a characteristic impedance (Zo) based on geometry and dielectric around the conductor and return path. For an in-depth review of transmission line, please refer some excellent references as given at the end.

In any simulation we need to build confidence on the models given. One way to do this is find solution of easy problems by hand for cases a formula or numerical values can be derived and then compare them with results from simulation. Once 100% agreement is established, one can go beyond simple situation and start modeling real world effects. In the case of transmission line, let’s look at 4 simple but common cases, where a 50Ω T-line is driven by a CMOS driver with 5Ω source impedance (typical for newer drivers) with an open load, short load, 100Ω load and a properly terminated 50Ω load. 

For each case, we will look at the load voltage waveform using bounce diagram. If you haven’t learned or played with bounce diagrams, do not fret, we will walk through it step by step.

First case: Load = Open or Hi-Z

For an open load situation, let’s start to build a bounce or reflection diagram for the below open circuit:

Screen Shot 2019-08-26 at 8.42.32 PM.png

Figure 2: CMOS driver with low impedance driving 50Ω line with no load.


  1. In any circuit, there is signal path and return path which is as important as signal path.
  2. After the long time meaning several transit time (TD) has been passed, T-line has becomes ideal and since load is open or Hi-Z, voltage at VL will approach 3.3V, after all it’s an open and no current can flow.
  3. Getting to final 3.3V would take several TD (illustrated below by creating bounce diagram step by step section and LTspice simulation).
  4. Reflection coefficients at load and source are calculated in Figure 3.
  5. Reflection coefficient is 1 for an open load case. A

Screen Shot 2019-08-29 at 8.54.09 AM.pngFigure 3: Formula and calculation of Reflection at source and load.

Building Bounce Diagram one TD a time:

Bounce or reflection diagram consist of two axises. Horizontal axis represent location on transmission line and goes from z=0 to z=d where d is actual length of transmission line. Vertical lines represent time and marked as in unit of time delay (TD).  We draw a first line representing the signal launched into transmission line. Note V+  and I+ represent the initial waveform voltage and current signal. These signals encounter the impedance of the line, in this case 50Ω. V+ is calculated using the voltage divider formula as 3.3V(50Ω/(50Ω+5Ω)) = 3V and I as  V+/Zo. 

Similarly V and I show reflected voltage and current waveforms respectively. These are calculated using Load reflection coefficient. Similarly V++ and I++ are calculated using generator reflection coefficient and represent reflected waveforms from source after 2 TD. The “tennis match” continues as illustrated in the series of diagrams below:

Screen Shot 2019-08-26 at 8.55.27 PM.png

Screen Shot 2019-08-26 at 9.15.45 PM.png

Screen Shot 2019-08-26 at 9.21.38 PM.png

Screen Shot 2019-08-26 at 9.22.22 PM.png

Screen Shot 2019-08-26 at 9.23.07 PM.png

Screen Shot 2019-08-26 at 9.24.19 PM.png

Figure 4: Building up the bounce diagram

I intentionally picked this example as source and load side impedances are severely mismatched. In-fact load is open with infinite resistance. I think we have enough data to make comparison with LTspice. Here is the load voltage waveform by hand if you were to put an oscilloscope at the load side, this is what we will measured. Of-course, this is not complete as final value should be 3.3V, but it will take several more bounces before it reaches this value, but we let LTspice handle it.

Screen Shot 2019-08-26 at 9.29.59 PM.png

Screen Shot 2019-08-26 at 9.31.07 PM.pngScreen Shot 2019-08-26 at 9.31.34 PM.png

Screen Shot 2019-08-26 at 9.38.28 PM.png

Screen Shot 2019-08-26 at 9.38.52 PM.pngScreen Shot 2019-08-26 at 9.39.10 PM.png

Figure 5: Building up the load voltage waveform

Here are LTspice results:

Screen Shot 2019-08-27 at 11.15.56 AM.pngScreen Shot 2019-08-27 at 11.18.21 AM.png

Figure 6: LTspice simulation for open load transmission line

As marked on the waveform, first 6 Time Delay (TD) values are agreed 100% to our calculated values. But notice that it takes several bounces back and forth actually more than 50ns before a steady state value of 3.3V reached. First time I learned this it was really surprising, but it is a direct consequence of finite speed of light and mismatch between source and load impedance.

Second case: Load=0Ω or short

Second interesting case is when load is shorted after the transmission. Since load is shorted, output voltage should be zero, but it will be current that will build up to its final value according to ohm law, I = 3.3V/5 = 0.66A.

Screen Shot 2019-08-30 at 11.40.27 AM

Figure 7: Transmission line for shorted output,  note very small value of resistance is used for probing otherwise LTspice won’t give us the current waveform at the load.

Let’s calculate first few TD using the bounce diagram and then we let LTspice calculate the rest of it.

Screen Shot 2019-08-30 at 11.51.50 AM.png

Screen Shot 2019-08-30 at 11.52.53 AM.png

Figure 8: Bounce diagram and current waveform. y-axis is current in Amp and x-axis is time in unit of TD. 

Here are LTspice results. Note the agreement between calculated and simulation values. One thing to note is that since we used a very small resistance (just think of resistance of the wire) at the output, voltage will be also climb up like this which you can easily verify it using the attached simulation files.

Screen Shot 2019-08-30 at 12.00.26 PM.png

Figure 9: Simulation results of shorted load

Third case: Load=100Ω

This is a typical case where where T-line is driving 50 ohm line with load impedance of 100Ω. Screen Shot 2019-08-30 at 11.44.30 AM.png

Figure 9: 50Ω Transmission line driving a 100Ω load

Here is the bounce diagram and LTspice simulation results for this case:

Screen Shot 2019-08-30 at 12.09.33 PM.png

Screen Shot 2019-08-30 at 11.44.16 AM.png

Figure 10: 50Ω Transmission line driving a 100Ω load and its bounce diagram and LTspice simulation results

Fourth case: Load=50Ω

If load is matched with characteristic impedance there will be no reflection and perfect matching will occur. In-fact this is one of a termination scheme in the high speed digital logic circuits. Bounce diagram is very boring, but it show after 1 time delay of latency signal will reach its equivalent value of 3.3*(50/55)=3V. Notice this 50Ω termination has reduce the output voltage by 300mV and will eat up the noise margin. Also, high power consumption is the second factor with this scheme. That’s why other termination schemes are typically employed but this topic warrant its own post.

Screen Shot 2019-08-30 at 11.46.36 AM.png

Figure 10: 50Ω Transmission line driving a 50Ω matching load

Here is the bounce diagram:

Screen Shot 2019-08-30 at 12.22.34 PM.png

Screen Shot 2019-08-30 at 11.46.44 AM.png

Figure 10: 50Ω Transmission line driving a 50Ω matching load, output voltage, after 1ns of TD, reaches is final value of 3V.

In essence, learning any simulation tool is basically checking fundamental equations and methods against it. Only then one can advance to more complicated and real-world modeling. Hope this post not only show how to simulate transmission line but gives out a good refresher on bounce diagram. Please feel free to post any comments, I will continue to improve on these lessons. Next lesson: Generate Electronic Sources.

Download LTspice file: Tline_3_cases.asc


Gregory D. Durgin, Andrew F. Peterson, Transient Signals on Transmission Lines: An Introduction to Non-Ideal Effects and Signal Integrity Issues in Electrical Systems, ISBN-10: 1598298259

Bogatin, Eric Signal and Power Integrity – Simplified (3rd Edition), ISBN-10: 013451341X

If you want to discuss it then jump here:

Posted in LTspice for EE students | Leave a comment

LTspice Lesson 2: Node Voltage and Mesh Current Analysis using LTSpice

LTspice command: .op

Node voltage and Mesh current are methods that systematically calculate voltages and currents in a circuit. Although LTspice calculate voltages and currents by using sophisticated network theory, but nonetheless, it can be useful to match the node voltages and mesh currents with hand calculation as required to do so in a first year elementary circuit courses. Mesh current and Node voltage examples here are purely for academic purpose. The goal here is to introduce .op command. It perform a dc operating point analysis and calculate all the node voltages and branch currents in a given circuit. 

Following simple circuit is used to illustrate the mesh current analysis by hand:

Screen Shot 2019-07-22 at 11.03.32 AM.png

To get mesh currents from the Ltpsice .op analysis, one has to make sure to get the branch current that is isolated and matches with its mesh current counterpart. For example, current going through 10V source is same as mesh current I1 except polarity is reversed. This is because LTspice takes the current direction into the voltage source. Here is LTspice example for the above hand analysis.

Screen Shot 2019-07-19 at 5.50.01 PM.png

Here is the simple node voltage analysis of the same circuit. Reading the node voltage in LTspice is exactly the same as node voltage calculation by hand given reference node is the same in both cases.

Screen Shot 2019-07-22 at 11.03.37 AM.png

To sum up, the point of this post was to illustrate .op spice statement and how it can calculate dc voltages and currents in a give circuit topology. As an example, Mesh current and Node voltage methods were used in a simple circuit.

If you want to discuss it further, please jump here:

Posted in LTspice for EE students | Leave a comment

Why I returned my 2019 Tesla Model X?

IMG_5933Kids and we were very excited that we bought Tesla Model X (Long range with Full Self-Driving Capability) which was delivered to our door on June 18, 2019 in our Sunnyvale, CA house. In-fact our whole extended family including our parents were excited. They have never seen a car like that with Falcon wings and self-driving capability. Following Sunday, we took the car from Sunnyvale to Sacramento to visit our parents. While driving the car, I noticed a faint high pitch sound coming from front of the car. I immediately turned to my wife sitting next seat to confirm if she can hear it as well, she nodded. We tried to ignore it first by playing some music, and it seemed to get diminished. Noise was more prominent at higher speed from 60-80 mph range, but at lower speed it was barely noticeable. On the way back from Sacramento, the constant high pitch caused me a major headache. I decided to record it using my iPhone. Later I sent the recording to our Tesla representative, Mike Dao. From the beginning Mike has been very professional, quick to response and one point contact. “That doesn’t seem normal.” he replied quickly and suggested that bring the car to have a technician look at it. 

My wife brought the car to Tesla Fremont Center; they confirmed this is normal as it is a dual motor vehicle with one motor in the front, High pitched noise is caused by the current that motor demands. 

As a working hardware engineer professional, that explanation made sense to me, but found it totally unacceptable and disturbing that high pitch sound in the cabin supposed to be “normal” and Tesla do not have any fix for it. From my working experience in audio, I knew that noise frequency seems to be in 4kHz to 5kHz range. Since I have done the recording earlier, I decided to ran some FFT (Fast Fourier Transform) to isolate the noise frequency using a software tool called Adobe Audition.  FFT clearly show approximately 4kHz spike. Even though magnitude doesn’t seem that big but it is significant enough that if you have sensitive ears and listen to it constantly you will get annoyed pretty quickly. 

Spectrum of audio recording while driving on 1-80W toward San Francisco. Speed approximately 60 mph.

Screen Shot 2019-07-04 at 5.50.01 PM

You can also listen to the actual audio I recorded in the cabin while driving:

In conclusion, we loved the car features and wished Tesla has some solution to fix this problem. Honestly, this car is a step forward in the entire car history, and we would strongly consider it again once all these annoying little issues gets ironed out.

Interesting discussion on this topic is here:


Posted in 5 Hi-Tech Silicon Valley Tour | 5 Comments

Unconventional guide to becoming a leader and being a leader

Kashif Javaid

I recently took Advanced Leadership class in Santa Clara University as a part of my MSEE program. Class discussion took turn from conventional view of becoming a leader to philosophical yet practical view. Becoming a leader and being a leader are two distinct traits. In this post I will share my final paper. I believe it will make you think if leaders like Ghandi, Hitler or Mandela were born leader or they actually cultivated some leadership skills or perhaps they were just there at the right time. In the end, I came up with 5 leadership strategies to become a leader in your chosen field.

Becoming a leader involves tailer to the need of followers and provide a common vision but it involves much more. In fact, whether ethical or not, leadership comes with certain leverage where if leader runs into a wall, people following him or her will do so as well. Now there is more at stake and leadership comes with certain responsibility. Before an actor act for his or her role in a movie, they have to study the character, dress, walk, and talk like a character, in short, become a character. In-fact, becoming a leader is similar to becoming an actor. 

Screen Shot 2019-03-28 at 10.00.44 AM

In essence, becoming a leader requires an ability to read perception of target followers and adapt behaviors that correspond to desired perception. History is littered with leaders where they went in great length to create a perception that followers perceived. For-example, Hatshepsut, one of ancient Egypt’s first female rulers, chose to wear false beard along with masculine attire to preserve the status quo of that time and to become leader of her people. From the history channel website, “As pharaoh, Hatshepsut undertook ambitious building projects, particularly in the area around Thebes. Her greatest achievement was the enormous memorial temple at Deir el-Bahri, considered one of the architectural wonders of ancient Egypt. Another great achievement of her reign was a trading expedition she authorized that brought back vast riches–including ivory, ebony, gold, leopard skins and incense–to Egypt from a distant land known as Punt (possibly modern-day Eritrea).” [1] I argue that she accomplished all the above great feats by catering to the need to her followers and creating perceptions that followers demanded.

Being a leader is completely different phenomena than becoming a leader. Being a leader is all about developing an ability to seeing reality as it ‘is’. This cannot be taught in few days and may take a lifetime to develop it. The main thing is to develop an awareness that ability to see things as they ‘are’ really distorted by our intellectual, emotional and biological obstacles. 

Intellectual obstacles are beautifully captured by Kahneman book: Thinking Fast and Slow. Although the book discusses many heuristics, some tries to explain why our ability to see things can be distorted. In the heuristics, confidence over doubt, Kahneman assert, “When we detect what appears to be a rule, we quickly reject the idea that the process is truly random” [2] Since our brains are wired with pattern recognition, we tend to attribute causality where none exist. Our memories are fallible, but we tend to rely on it when a critical decision needs to be made. We are more suggestible than we are actually aware of. This is really important point because this could directly distort reality. 

Emotional obstacles are captured by Steinbeck book: Log from the Sea of Cortez. In his essay, he states: 

“But the greatest fallacy in, or rather the greatest objection to teleological thinking is in connection with the emotional content the belief. People get to believing and even to professing the apparent answers thus arrived at, suffering mental constrictions by emotionally closing their minds to any of the further and possibility opposite “answers” which might otherwise be unearthed by honed effort—answers which, if faced realistically, would give rise to – struggle and to a possible rebirth which might place the whole problem in a new and more significant light.” [3]

This one paragraph allude to a mental state when conflicting with a situation we tend to believe in an apparent first answer and eliminate tension with an alternative situation that might exist in the brain. The only way to see beyond the first thought is to stick with contradictions that arrises and create a mental leap where one take oneself out of the situation and reality or situation being observed unwind itself to present its true nature. 

Biological obstacles are discussed in the paper by Churchland, Ramachandran, and Sejnowski: A Critique of Pure Vision. The main premise is that we are hardwired in our brain to detect pattern where none exists and can be easily fooled by randomness. Essay further discusses how our biology hinders our ability to see reality which beautifully concluded by the essay:

“Obviously visual system evolved not for the achievements of sophisticated visual perception as an end in itself, but because visual perception can serve motor control and motor control can serve vision to better serve motor control, and so on. What evolution “cares about” is who survives and that means, basically, who excels in the fours Fs: feeding, fleeing, fighting and reproducing” [3]

Thus, our biology really distort the reality we actually see. Since being a leader requires the ability to see things as they are, so what can we do to overcome these limitations?

The only way to really know you are developing an ability to see things as it “is” that you have sincere and authentic humility growing deep within you. This is completely opposite of arrogance which blocks one’s ability to see the things as it “is”.

The  solution is to use of Hegalian dielectric thinking combined with emotional management. The gist is that once one has abstracted an idea and after developing some humbleness and staying with the idea long enough to create a tension, one reach a Aufhebung, a german word for sublation or overcoming. In this stage one let go of his or her bias and perceive reality as “is” rather than obscured by thoughts, bias and prior history and experiences. This is a broad topic and beautifully captured by Pravin Jain article, “A framework for embodying emergence in visioning. Emergence: Complexity and Organization [5]”

In summary, below diagram illustrate that a transition from becoming a leader to being a leader is bit like growing a tree where right ingredients such as directly asking questions to potential followers, by body techniques that followers value in the leadership, creating a track record or perception of it, but most importantly by quiet observation, reading and listening accurately what followers values and judges in a leader are needed to become a leader. But being the leader and ability to perceive reality is bit like sitting on the canopy where vision is clear of any branches, leafs or any other objects in the forest.

Screen Shot 2019-03-28 at 10.03.36 AM.png

5 Leadership Strategies:

Throughout the course, I was able to glean out some strategies which I will be personally using at my work and home to become an effective leader. Here are a list organized by the most important trait to the least important trait, but are keys to be an effective leader:

  1. Acknowledge and recognize personal paradigms that limits oneself to see what things actually are.
  2. Become aware of intellectual, emotional and biological obstacles to seeing the actual reality and develop a genuine humility from what we do not know, but also what we cannot know.
  3. Being more observant, study potential followers, a bit like when actor prep for his role.
  4. Create track records, work on body language, improve speech and presentation skills.
  5. Do not hesitate to engage in a struggle and learn to bring an order in seemingly chaotic group of potential followers.


  2. D. Kahneman, (2011), Thinking, Fast and Slow. Farrar, Strauss and Giroux, New York
  3. J. Steinbeck, (1995) The Log from the Sea of Cortez. Penguin Classics
  4. P.S. Churchland, V. S. Ramachandran, and T.J. Sejnowski, (1994), A Critique of
    Pure Vision. The MIT Press Cambridge, Massachusetts London, England 
  5. Jain P. Leadership and Steinbeck’s ‘non-teleological thinking’: A framework for embodying emergence in visioning. Emergence: Complexity and Organization. 2017 Dec 31.


Posted in 5 Hi-Tech Silicon Valley Tour | Leave a comment

LTspice Lesson 1: Generating IV curves

Kashif Javaid

“Never perform a measurement or simulation without first anticipating the results you expect to see.” ~Eric Bogatin’s Rule # 9

Learn these spice commands: .dc .param

In these 10 lesson series, we will explore LTspice circuit simulator. Assumption is that you’re a beginner or someone who already plays around with it a bit and feel it has potential to solve circuit problems, and perhaps provide intuition and insight how electronic circuits works. Ultimately, it will help solve a real world EE problem and continue to provide a quick go to tool for a quick circuit simulation of some proof of concept.

The approach we will take is that we will never simulate a circuit unless we know what output we expect to see. This is beautifully captured by world-renowned signal integrity expert Eric Bogatin rule # 9. [1]

First of all, why start with IV curves? Voltage-Currrent (aka IV) relationship of a component can tell us a lot about behavior of that component. In a nutshell, by applying a voltage across its terminal and measuring the resulted current, one can figure out the resistance or more generally impedance of the component. Later this knowledge can lead to electrical models which can help design and predict the behavior of a circuit. This  is a good starting point as we will get to know immediately two of most important LTspice simulation commands: .dc and .param

We will look at IV curves of following components:

  1. Resistor
  2. Diode
  3. NPN and PNP BJT
  5. Solar cell

We will be using following 5 steps approach for each of the circuit in these tutorials:

Step 1: Draw a circuit. 

Step 2: Add proper dot simulation command.

Step 3. Predict its behavior.

Step 4: Simulate and verify behavior with your prediction.

Step 5: (Optional) Repeat step 3 if result doesn’t match prediction and extend the example for some other use case or different parameters.


Let’s start things with a lonely resistor and it’s IV curve. True to rule # 9, a resistor is related with voltage and current through ohm law: V=I*R or I = V / R. This is in the form of y = m*x form where m = 1/R is the slope. So if we vary a voltage from 1V to 2V we expect to see a current proportional to 1/R. This means if resistor is huge (i.e ~MΩ range), current would be small compared to if resistor is small (i.e ten’s of ohm). Let’s see if we can verify it using LTspice.

Step 1:

I am not going to layout exact steps for how to find these components. Just mess around and find them yourself and wire it up like this. Tip, you can find most of generic component in this toolbar link:

Screen Shot 2019-02-03 at 10.58.28 AM

*If you want to take a short cut, you will find all the .asc files at the end.

Here is a simple schematic where resistor and voltage source are wired as below. Note the variable X in curly bracket. We will use it to vary the value of R1.

Screen Shot 2019-02-03 at 1.25.21 PM

Step 2:

We will start with following two simulation commands: .dc and.param

.dc V1 Lin -10 10 .1

The syntax is almost readable and follow the format of .dc <Voltage or Current source> <Start value> <Stop Value>  <increment>. In this case we want to sweep voltage source V2 linearly from -10V to +10V with increment of 100mV. Ltspice provide a useful dialog box which can also be used enter these values:

Screen Shot 2019-02-03 at 1.29.29 PM.png

Now let’s a take a look at this command

.step param X list 100 1k

Again the syntax is readable and allow a source or parameter to vary by a list of values or some increment. In this case, we want to step our X variable which correspond to R1 value in the schematic for two values 100Ω and 1kΩ.

Step 3: 

As mentioned earlier, low value resistor will be able to pass lot more current and curve will be close to current axis in accord with the ohm law. A high value resistor will pass low current thus its curve should be close to voltage axis.

Step 4:

Run the simulation with clicking on the running man in the tool bar: Screen Shot 2019-02-03 at 1.37.17 PM.png. After simulation run without an error, point the cursor on the resistor until a current probe appears and click it. This will plot voltage vs current plots on the plot window with two defined resistor values:

Screen Shot 2019-02-03 at 1.40.54 PM.png

Notice as expected R1=10Ω is close to current axis when compared with R1=100Ω as we have predicted from the ohm law. Granted this is a extremely simple example, but it will help with more complicated circuit in which reasoning remain the same but formula gets more complex.

Step 5:

Let’s go one step further and create IV curves by varying R1 from 1Ω to 100Ω with increment of 1Ω. How does the .param command will change? How long it takes for simulation to plots these curves? I will leave this as an exercise, but prediction remain the same and curves are shown below: Actual simulation file .asc attached if you want to play along. R_IV_2.asc

Screen Shot 2019-02-03 at 1.55.52 PM.png


Step 1 and 2:

Screen Shot 2019-02-03 at 7.48.09 PM.png

Step 3:

Lets add a .dc command to simulate diode IV. Notice, 1N4148 is real diode, but it should follow diode equation:

Screen Shot 2019-02-18 at 3.48.09 PM.png

We expect to see an exponential curve as we vary VD. Click on the diode when cursor become a current probe to following plot:

Step 4:

Screen Shot 2019-02-18 at 3.51.42 PM.png

Notice, VD can be varied at any arbitrary voltage, but since this is a real diode it adheres to absolute maximum rating as per its datasheet:

Screen Shot 2019-02-18 at 4.02.09 PM.png

Simulation gives a false sense of putting any voltage across diode, but in-fact if power dissipation gets exceeded, expect to see smoke in a real circuit build. LTspice won’t gives any warning. It is your job as a circuit designer to adhere to any datahseet limits.

Step 5:

Let’s extend the above example to simulate the effect of temperature. As diode equation predict and both VT and Is are function of temperature, we expect to see at higher temperature current rise earlier than room temperature. In order word diode will switch faster. As an example add following command to effect of temperature on this real world diode.

.step temp list -40 25 85

Screen Shot 2019-02-18 at 4.15.02 PM.png


From this point on, I will combine all the steps here. Since a transistor is 3-terminal device, you have to make the one terminal constant current or voltage value while varying the other one. For typical IV curves, we make the base current constant while varying the VCE of the transistor. Then we can do it for multiple value of base current. The .dc command shown below the circuit. We expect to see a triode region and saturation region.


Screen Shot 2019-02-25 at 9.18.10 AM.png


Screen Shot 2019-02-25 at 9.18.58 AM

Screen Shot 2019-02-25 at 9.21.56 AM.png


Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

Screen Shot 2019-02-25 at 9.46.19 AM.png

Note the convention used above where PMOS is source is tied to highest positive rail.

Screen Shot 2019-02-25 at 9.45.46 AM.png

Screen Shot 2019-02-25 at 9.47.58 AM.png




An excellent paper that discusses the solar cell simulation using datasheet parameters is given below.

Simulation of Single-Diode

A simplified Rseries and Rshunt model of solar cell is given below. Just click on the V1 while cursor in current probe mode to run the simulation.

Screen Shot 2019-02-25 at 10.48.17 AM.png

Screen Shot 2019-02-25 at 10.48.27 AM.png



This just scratches the surface of LTspice capability and a good starting point to get familiarize with some basic commands. Next tutorial will focus on DC circuit analysis.

If you want to discuss it further, please jump here:





Posted in LTspice for EE students | Leave a comment

Tales of a system design that worked

Screen Shot 2018-01-29 at 10.58.33 PM.png

Early in my career at National Semiconductor (now merged with Texas Instrument), we were spitting out 7+ different audio chips each quarter in a fiscal year. Some of them were brand new design or some were just a little tweak such as addition of a small feature i.e low power or shutdown mode. Typically, these chips came in with different packages from microSMD to DIP. With handful of application engineers and test engineers always needed more time, the challenge was how to characterize these chips on time with better efficiency. My application manager at that time, Jeff Bridges, came up with a solution: simply to build automation test system using Audio Precision as the brain of the system (now a standard tool to test audio performances of almost any audio system and chips) with GPIB (General Purpose Interface Bus) equipped power supplies, data acquisition units, function generators, and a digital oscilloscope. (simple block diagram block shown below). Not just build one, but build 10 of these systems to support different regions in the world that are doing manual audio testing for our products. Screen Shot 2018-01-29 at 10.43.54 PM

I was chosen as the lead hardware and software engineer. As a newly graduated EE, I was eager to take in the big responsibility, but this turned out to be no joke at all. As most people in the group weren’t software engineer, I was left alone to figure out how the whole system supposed to interface with hardware and software. With time clock started ticking, myself and my technician at the time, started the daunting job. Luckily, technician, Orville has tons of experience building cabling and test racks, while he started on purchasing equipments and cabling, I went to white board and started brainstorming, how the boards and daughter card should looks like? Schematics were drawn in Protel (now Altium). I started working on the layout of the motherboard and daughter cards. The idea was that we will have one giant (12”x8”) motherboard with relays to route different audio test paths with interface pins which connect to test rack. After that I focused on the software aspect, the audio precision used at that time supported built in visual basic programming; this became the logical choice to automate other instruments as well. It turned out that VB is a great scripting language to control GPIB capable instruments. The only thing was that libraries have to be written from scratch for each instrument. For example, in order to set voltage and current for a power supply or capture a scope shot with a required relays configuration, raw SCPI commands from these instruments has to be properly captured and then wrap around on user friendly functions. The whole project needed several files linked together in the main program. The good portion of the year went by and finally we were able to characterize numerous products including LM4930.

The LM4930 is an integrated audio subsystem that supports voice and digital audio functions. The LM4930 includes a high quality 16 bits I2S input stereo DAC, a voice band codec, a stereo headphone amplifier and a high-power mono speaker amplifier. I believe it is still in production as of today by Ti despite the fact, they have closed the audio group.

As a first big project, I really enjoyed the whole system experience from idea to actually building the test system (a picture of this test system shown above). Another happy side effect came out when datasheet electrical table entirely can be produced with one command. Various performance curves now be generated much faster than on the bench. Soon it became part of a regular project development cycle where product and other application engineers used this test system on a regular basis.

One of the main lesson that I learned was that during development of layout and design, it is best to engage relevant people early on where they can chime in their expertise before you send the board to fab. For example, I did the routing of some of amplifier control lines without 50 ohm impedance matching. Even though, SPI interface can be run at lower frequency, but at 24MHz, it needs proper termination and controlled trace impedances. This ended up being requiring spin out of a new version of the daughter board.


Posted in Automation | Leave a comment